With the trend toward a ubiquitous network and wearable mobile equipment, the market is strongly demanding that LSIs and memory devices exhibit higher speed operation, higher integration and lower power consumption. According to the International Technology Roadmap for Semiconductors (ITRS2001), alternation of design rule generations will be accelerated and, as well, introduction of new materials and structures will start being accelerated at a node below approximately 65 nm node. One of the causes of such acceleration is that it has become more difficult to obtain satisfactory current driving ability than before due to source voltage scaling, deterioration of carrier mobility and the like. In attempt to solve these problems, proposals have been made of a device in which a new material having a high carrier mobility such as strained silicon or silicon-germanium (SiGe) is introduced to form a channel (see J. L. Hoyt and seven others, “Strained Silicon MOSFET Technology”, International Electron Device Meeting (IEDM) 2002, P23-26 for example) and of a device having a three-dimensional channel structure such as a fin FET (Fin Field Effect transistor (trigate)) or a double gate device (see Japanese Patent Publication No. 2768719 for example).
Silicon-germanium has a higher carrier (hole) mobility than silicon. For this reason, the use of silicon-germanium for the p-channel of a field effect transistor makes it possible to realize a higher speed operation. On the other hand, strained silicon is higher in both electron mobility and hole mobility than silicon having no lattice strain. Accordingly, the use of strained silicon for both of n- and p-channels of field effect transistors makes it possible to improve the performance of the transistors, hence, realize a higher speed operation without relying upon miniaturization. However, under acceleration of miniaturization it becomes very difficult for such conventional transistor structures to suppress the short channel effect.
The short channel effect is a phenomenon which becomes conspicuous when the drain becomes more dominant over the channel than the gate (specifically, when a depletion layer extending from the drain exerts an influence upon the formation of the channel) and which causes fluctuations in the threshold value of the transistor and an increase in leakage current to occur. Each of the transistors called the fin FET and the double gate transistor, which have been proposed in attempt to overcome this problem, has a structure wherein the channel is three-dimensionally surrounded by the gate to enhance the dominance of the gate over the channel. Accordingly, the channel is applied with the gate voltage from at least two directions whereby the short channel effect can be suppressed effectively. At the same time, such a transistor has a gate-surrounded channel area two to three times as large as that of a full depletion type device having a two-dimensional (planar) gate structure per unit device area and hence has increased current driving ability. However, because such a proposed device has the channel formed of conventional silicon, the challenge to improve the driving ability from the viewpoint of deterioration of carrier mobility is left unsolved.